The present invention relates to a semiconductor design technology, and more particularly, to a high-integrated semiconductor memory device including a plurality of memory banks and various internal circuits for performing the input/output operation of data and internal structure thereof.
Generally, a semiconductor memory device including a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), for example, stores or outputs data according to a command required by a central processing unit (CPU). In a case where the CPU requires a writing operation, the semiconductor memory device stores data in a memory cell corresponding to address information input from the CPU. In a case where the CPU requires a read operation, the semiconductor memory device outputs the data stored in the memory cell corresponding to the address information input from the CPU.
The semiconductor memory device includes ten millions or more memory cells, and a set of the memory cells generally is called a memory bank. That is, the memory bank includes a plurality of memory cell arrays. The number of memory banks included in the semiconductor memory device may be changed according to design, but the number of the memory banks is increasing recently for the large-scaling of the semiconductor memory device.
FIG. 1 is a block diagram illustrating some configuration of the existing semiconductor memory device, and illustrates a DRAM including four memory banks as an example.
Referring to FIG. 1, the semiconductor memory device includes zeroth to third memory banks 110, 130, 150 and 170 disposed in a core region, and a control signal generation unit 190 patched in a peripheral region other than the core region, i.e., a peripheral region.
For convenience, the following description will be made on configuration corresponding to the zeroth memory bank 110 as a representative example.
The zeroth memory bank 110 is activated in response to a zeroth bank active signal RBKA<0>, and includes a plurality of memory cell arrays (not shown) storing data, a zeroth sense amplification unit 112 sensing and amplifying data corresponding to a memory cell selected by the zeroth bank active signal RBKA<0> among a plurality of memory cells in the zeroth memory bank 110, and a zeroth delay 114 delaying the zeroth bank active signal RBKA<0> by a predetermined time to generate a zeroth operation control signal SAC0<0>.
Herein, the zeroth bank active signal RBKA<0> is generated in a bank control signal generation unit 192, and is a signal activated upon the active operation of the zeroth memory bank 110. The zeroth sense amplification unit 112 operates according to the zeroth operation control signal SAC0<0> where the zeroth bank active signal RBKA<0> has been delayed by the predetermined time. Subsequently, a time delayed by the zeroth delay 114 is controlled by delay control signals DLC<0:N> (N is a natural number) generated by a delay control signal generation unit 194.
The first to third memory banks 130, 150 and 170 have configuration similar to that of the zeroth memory bank 110. The first to third memory banks 130, 150 and 170 perform active operations in response to corresponding first to third bank active signals RBKA<1> to RBKA<3>, respectively. First to third delays 134, 154 and 174 receive the first to third bank active signals RBKA<1> to RBKA<3> to delay them by a time corresponding to the delay control signals DLC<0:N>, and generates zeroth operation control signals SAC0<1> to SAC0<3> corresponding to respective first to third sense amplification units 132, 152 and 172. Herein, the number of the zeroth operation control signals SAC0<0> to SAC0<3> corresponding to the respective zeroth to third sense amplification units 112, 132, 152 and 172 may be changed according to the operation of the sense amplification unit.
The control signal generation unit 190 includes a bank control signal generation unit 192 generating the zeroth to third bank active signals RBKA<0:3> for selecting any one of the zeroth to third memory banks 110, 130, 150 and 170 in response to an external address, and a delay control signal generation unit 194 generating the delay control signals DLC<0:N> for controlling a time delayed by the zeroth to third delays 114, 134, 154 and 174 upon a test mode.
FIG. 2 is a waveform diagram describing the operation waveform of the semiconductor memory device of FIG. 1. It is assumed that the number of operation control signals for controlling the zeroth to third sense amplification units 112, 132, 152 and 172 is 2, respectively. In other words, the zeroth operation control signal SAC0<0> and a first operation control signal (hereinafter, SAC1<0>) exist in correspondence with the zeroth sense amplification unit 112, the zeroth operation control signal SAC0<1> and a first operation control signal SAC1<1> exist in correspondence with the first sense amplification unit 132, the zeroth operation control signal SAC0<2> and a first operation control signal SAC1<2> exist in correspondence with the second sense amplification unit 152, and the zeroth operation control signal SAC0<3> and a first operation control signal SAC1<3> exist in correspondence with the third sense amplification unit 172. The delay control signals DLC<0:N> will not be considered in FIG. 2.
Referring to FIGS. 1 and 2, when a zeroth bank active signal RBKA<0> is activated from a logic low level to a logic high level, the zeroth delay 114 delays the zeroth bank active signal RBKA<0> by tD1 to generate the zeroth operation control signal SAC0<0> corresponding to the zeroth sense amplification unit 112, and thereafter delays the zeroth operation control signal SAC0<0> by tD2 to generate the first operation control signal SAC1<0> corresponding to the zeroth sense amplification unit 112. In this way, the generated zeroth and first operation control signals SAC0<0> and SAC1<0> control the zeroth sense amplification unit 122.
In a case of the DRAM as illustrated in FIG. 1, the zeroth to third memory banks 110, 130, 150 and 170 may simultaneously perform an active operation, and the word line (not shown) of a corresponding memory bank is enabled in response to the selected zeroth to third bank active signals RBKA<0:3>. When the word line is enabled, the data of a memory cell connected to the word line is transferred to a corresponding sense amplification unit, and the sense amplification unit senses the data to perform an amplification operation. At this point, the sense amplification unit is controlled by the zeroth and first operation control signals generated through the delay of a corresponding bank active signal.
FIG. 3 is a block diagram illustrating some configuration of the existing semiconductor memory device, and illustrates a Phase Random Access Memory (PDRAM) including four memory banks as an example.
Referring to FIG. 3, the semiconductor memory device includes zeroth to third memory banks 310, 330, 350 and 370 disposed in a core region, and a control signal generation unit 390 patched in a peripheral region.
For the sake of convenience, the following description will be made on configuration corresponding to the zeroth memory bank 310 as a representative example.
The zeroth memory bank 310 is activated in response to a zeroth bank active signal RBKA<0> and a zeroth programming active signal PBKA<0>, and includes a plurality of memory cell arrays (not shown) storing data, a zeroth sense amplification unit 312 sensing and amplifying data corresponding to a memory cell selected by the zeroth bank active signal RBKA<0> among a plurality of memory cells in the zeroth memory bank 310, and a zeroth delay 314 delaying the zeroth bank active signal RBKA<0> by a predetermined time to generate a zeroth operation control signal SAC0<0>.
Herein, the zeroth bank active signal RBKA<0> and the zeroth programming active signal PBKA<0> are generated in a bank control signal generation unit 392. Among these, the zeroth bank active signal RBKA<0> is a signal that is activated for activating the zeroth memory bank 310 upon a read operation, and the zeroth programming active signal PBKA<0> is a signal that is activated for activating the zeroth memory bank 310 upon a programming operation.
Hereinafter, the following description will be made on a memory cell used in the PRAM for understanding the programming operation.
Generally, the semiconductor memory device including the PRAM is classified into a nonvolatile memory device standing comparison with a volatile memory device such as the DRAM, and consumes power less than the consumption power of the DRAM. Such a semiconductor memory device includes a phase change material in a memory cell for storing data. A widely known phase change material includes Ge—Sb—Te (GST) being the compound of germanium (Ge), antimony (Sb) and tellurium (Te). The phase change material is changed into two stable states by heating. That is, the phase change material has an amorphous state and a crystalline state.
Herein, the amorphous state is a state where the phase change material is heated for a short time at a temperature near to a melting temperature and thereafter is changed by rapidly cooling. On the contrary, the crystalline state is a state where the phase change material is heated for a long time at a crystallization temperature lower than the melting temperature and thereafter is changed by gradually cooling. The phase change material of the amorphous state has resistivity higher than the phase change material of the crystalline state. The memory cell represents a logic low data and a logic high data by using the properties of the phase change material. In this way, an operation of changing the phase change material into the amorphous state or the crystalline state calls a programming operation. The respective zeroth to third memory banks 310, 330, 350 and 370 perform the programming operation in response to zeroth to third programming active signals PBKA<0:3> corresponding to them, respectively.
As shown in FIG. 1, the semiconductor memory device of FIG. 3 controls the zeroth sense amplification unit 312 according to a zeroth operation control signal SAC0<0> where the zeroth bank active signal RBKA<0> has been delayed by a predetermined time. Subsequently, the delay time of the zeroth delay 314 is controlled by delay control signals DLC<0:N> (N is a natural number) generated by a delay control signal generation unit 394.
The first to third memory banks 330, 350 and 370 have configuration similar to that of the zeroth memory bank 310. The first to third memory banks 330, 350 and 370 perform active operations in response to corresponding first to third bank active signals RBKA<1> to RBKA<3> and first to third programming active signals PBKA<1> to PBKA<3>, respectively. Furthermore, first to third delays 334, 354 and 374 receive the first to third bank active signals RBKA<1> to RBKA<3> to delay them by a time corresponding to the delay control signals DLC<0:N>, and generates zeroth operation control signals SAC0<1> to SAC0<3> corresponding to respective first to third sense amplification units 332, 352 and 372. Subsequently, the first to third sense amplification units 332, 352 and 372 are controlled according to the zeroth operation control signals SAC0<1> to SAC0<3> corresponding to them, respectively. Herein, the number of the zeroth operation control signals SAC0<0> to SAC0<3> corresponding to the respective zeroth to third sense amplification units 312, 332, 352 and 372 may be changed according to the operation of the sense amplification unit.
The control signal generation unit 390 includes a bank control signal generation unit 392 generating the zeroth to third bank active signals RBKA<0:3> for selecting any one of the zeroth to third memory banks 310, 330, 350 and 370 and the zeroth to third programming active signals PBKA<0:3> for selecting the zeroth to third memory banks 310, 330, 350 and 370 to be programmed in response to an external address, and a delay control signal generation unit 394 generating the delay control signals DLC<0:N> for controlling a time delayed by the zeroth to third delays 314, 334, 354 and 374 upon a test mode.
As seen in FIGS. 1 and 3, although the PRAM and the DRAM have different configurations of the memory cells, since they have similar operations, configurations designed in relation with the characteristic of said each memory cell are designed differently from each other whereas configurations other than them are designed similarly to each other. Therefore, the design of the DRAM is considered upon the PRAM, or the design of the PRAM is considered upon design of the DRAM.
FIG. 4 is a waveform diagram describing the operation waveform of the semiconductor memory device of FIG. 3. It is assumed that the number of operation control signals corresponding to the zeroth to third sense amplification units 312, 332, 352 and 372 is 2, respectively. In other words, the zeroth operation control signal SAC0<0> and a first operation control signal (hereinafter, SAC1<0>) exist in correspondence with the zeroth sense amplification unit 312, the zeroth operation control signal SAC0<1> and a first operation control signal SAC1<1> exist in correspondence with the first sense amplification unit 332, the zeroth operation control signal SAC0<2> and a first operation control signal SAC1<2> exist in correspondence with the second sense amplification unit 352, and the zeroth operation control signal SAC0<3> and a first operation control signal SAC1<3> exist in correspondence with the third sense amplification unit 372. The delay control signals DLC<0:N> will not be considered in FIG. 4. Moreover, for the sake of convenience, the following description will be made on a case where the programming operation is performed in the zeroth memory bank 312 and the active operation is performed in each of the first and second memory banks 330 and 350 as an example.
Referring to FIGS. 3 and 4, the zeroth programming active signal PBKA<0> is shifted from a logic low level to a logic high level for performing the programming operation in the zeroth memory bank 310. In a case of the semiconductor memory device such as the PRAM, in an operation duration where the programming operation is performed in any one of the memory banks, the active operation of other memory bank may be performed. This is because the zeroth sense amplification unit 312 does not perform a sense amplification operation in a duration where the programming operation is performed on the zeroth memory bank 310. For reference, the programming operation is performed using a separate latch circuit, and the latch circuit has data information to be stored in the memory cell.
When the first bank active signal RBKA<1> is activated to a logic high level in correspondence with the first memory bank 330, the first delay 334 delays the first bank active signal RBKA<1> by tD1 to generate the zeroth operation control signal SAC0<1> corresponding to the first sense amplification unit 332, and thereafter delays the zeroth operation control signal SAC0<1> by tD2 to generate the first operation control signal SAC1<1> corresponding to the first sense amplification unit 332. In this way, the generated zeroth and first operation control signals SAC0<1> and SAC1<1> control the first sense amplification unit 332. Subsequently, the first bank active signal RBKA<1> is deactivated to a logic low level.
When the second bank active signal RBKA<2> corresponding to the second memory bank 350 is activated to a logic high level, the second delay 354 delays the second bank active signal RBKA<2> by tD1 to generate the zeroth operation control signal SAC0<2> corresponding to the second sense amplification unit 352, and thereafter delays the zeroth operation control signal SAC0<2> by tD2 to generate the first operation control signal SAC1<2> corresponding to the second sense amplification unit 352. In this way, the generated zeroth and first operation control signals SAC0<2> and SAC1<2> control the second sense amplification unit 352. Subsequently, the second bank active signal RBKA<2> is deactivated to a logic low level.
In a case of the semiconductor memory device exemplified in FIGS. 3 and 4, any one of the zeroth to third memory banks 110, 130, 150 and 170 performs the programming operation, and simultaneously the active operation of other memory bank is performed. At this point, the activation durations of the activated memory banks do not overlap with each other.
The semiconductor memory device is being further highly integrated, and efforts are being continuously made for decreasing a chip area in order to improve productivity. Actually, as the area of the semiconductor memory device decreases, the number of the semiconductor memory devices capable of being produced through one wafer increases, thereby enabling to save the manufacturing cost though the improvement of productivity. Hereinafter, the following description will be made on a semiconductor memory device capable of decreasing a chip area though the present specification.